Lpc2000

Hi Bill,

> Does this mean the entire Tx FIFO is empty? That is, I can write 16
> bytes to it whenever LSR:THRE is set?
> 
> Or, does it just mean that there's at least one byte of space available
> in the FIFO?

It means the entire Tx FIFO is empty.  Excerpts from LPC214x manual that
apply to the LPC213x:

Transmit Holding Register Empty (THRE)

"THRE is set immediately upon detection of an empty UART0 THR and is cleared
on a U0THR write."

"The UART0 THRE interrupt (U0IIR[3:1] = 001) is a third level interrupt and
is activated when the UART0 THR FIFO is empty provided certain
initialization conditions have been met. These initialization conditions are
intended to give the UART0 THR FIFO a chance to fill up with data to
eliminate many THRE interrupts from occurring at system start-up. The
initialization conditions implement a one character delay minus the stop bit
whenever THRE=1 and there have not been at least two characters in the U0THR
at one time since the last THRE = 1 event. This delay is provided to give
the CPU time to write data to U0THR without a THRE interrupt to decode and
service. A THRE interrupt is set immediately if the UART0 THR FIFO has held
two or more characters at one time and currently, the U0THR is empty. The
THRE interrupt is reset when a U0THR write occurs or a read of the U0IIR
occurs and the THRE is the highest interrupt (U0IIR[3:1] = 001)."


Joel