dodge1955 wrote:
> Can someone help me with this problem? See the code below. I have
> UART1 set up to print "Hello Test", but I can't get it to work with a
> 12Mhz clock, which is what is on the Eval boards. I am using
> currently the Embedded Artists board with the 12Mhz clock. If I set
> the U1DLL to 0x61, which is a 15Mhz clock, and leave VPBDIV = 0 (1/4
> processor clock) it works fine (as in the code below). If I set
> VPBDIV = 1 (equal to the processor clock), or if I set the U1DLL to a
> value for 12Mhz, it stops working. So, I guess I don't quite
> understand how all those registers work. Can someone explain? Is
> there something in the Startup code that overrides? Thanks.
>
> void set_up_uart1()
> {
> // VPBDIV = 1; // VPB clk (PCLK) same as processor clock (CCLK)
> PLL0CON = 0; // not using PLL, since PCLK = oscillator clock
> PLL1CON = 0; // not used
>
> PINSEL0 |= 0x00010000;
> PCONP |= 0x00000010;
>
> U1LCR |= 0x80; // enable Divisor Latches
> U1FDR = 0x00000010; // MULVAL = 1, DIVVAL = 0
> U1DLM = 0; // 15000000 / 9600 / 16 = 97 = 0x61
> U1DLL = 0x61; // 9600 baud, but at 15Mhz
> U1LCR = 0x03; // 8 bits, 1 stop, no parity, DLAB = 0
>
> U1FCR = 1;
I think the feed sequences for the PLLs are missing from your code,
so the writes to PLLxCON have no effect.
The things you describe can be explained by PLL0 staying at 60 MHz
from some previous initialisation, so PCLK would be 1/4th of that
at 15 MHz when VPBDIV=0.
By the way, there seems to be something odd in the baudrate calculation
formula given in the LPC214x user manual. The non-fractional part of the
baudrate is calculated as
PCLK/(16x(16xU1DLM + U1DLL))
Instead I would expect something like
PCLK/(16x(256xU1DLM + U1DLL))
because U1DLM and U1DLL are 8-bit values.
Regards,
BertrikMessage
Re: [lpc2000] VPBDIV register
2006-02-28 by Bertrik Sikken
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