Lpc2000

On Sunday 05 March 2006 17:36, Ake Hedman, eurosource wrote:
> "RM resets and disables
> much of the CAN Controller. Also at this time the Transmit
> Error Counter is set to 127 and the Receive Error Counter is
> cleared. Software must next clear the RM bit. Thereafter the
> Transmit Error Counter will count down 128 occurrences of the
> Bus Free condition (11 consecutive recessive bits). Software
> can monitor this countdown by reading the Tx Error Counter.
> When this
> countdown is complete, the CAN Controller clears BS and ES in
> CANSR, and sets EI in CANSR if EIE in IER is 1."
>
> That is your nodes need to see 128 correct frames after the
> bus off will be removed after you reset the RM bit. If all
> your nodes are at bus off that will not occur.

That do not mean, that you must have correct frames at the bus. 
This means, that you must have 128x a free/unused bus for the 
time of 11 bits. If no device transmit a message, the bus is 
recessive and the time is short. If other devices send messages, 
this 11 bits are the interframe space.

But this condition is only used from the CAN controller after a 
bus off, not after a Power on.

-- 
Steffen Rose
http://www.can-cia.org/dates/events/?212
CAN Wiki http://www.CAN-Wiki.info/