Lpc2000

--- In lpc2000@yahoogroups.com, "philips_apps" <philips_apps@...> wrote:
>
> Jaya,
> 
> I forwarded your question to the author of the FAQ because I do not 
> know the answer out of own experience. The Application Note makes 
> the clear statement that it is a general ARM7TDMI - VIC problem.
> For those interested in the detailled application note that 
> describes how to handle spurious interrupts:
> http://www.standardics.philips.com/support/documents/microcontrollers
> /pdf/an10414.pdf
> 
> We would however greatly appreciate if you would provide your 
> knowledge by investigating competitor devices using the VIC and 
> telling this community if this is not a general ARM VIC as stated in 
> the Application Note by running the same code on a competitor device 
> not showing the problem and on a LPC2000 device, showing the issue.

Hi Robert,

That is a fair challenge.

> We do experience the problem and consider it a general issue, not 
> specific to the LPC2000. If competitors do not mention it, it does 
> not mean it does not exist there. 

Right. And if ARM says: 
"If an interrupt is received by the core during execution of an
instruction that disables interrupts, the ARM7 family will still take
the interrupt. This occurs for both IRQ and FIQ interrupts."

The question is, since the pipeline is three-staged, at which point
the interrupt (IRQ/IFQ) is being sampled after fetch, decode or
execute cycle? I would imply int. sampling happens after execute.
Would someone clarify this ARM statement, please?
Thanks.

Best regards

Roger




> 
> Best regards, Robert
> 
> --- In lpc2000@yahoogroups.com, Jayasooriah <jayasooriah@> wrote:
> >
> > Dear Robert,
> > 
> > In the FAQ you referred to, on "ARM7DTMI-S Core", to the FAQ:
> > 
> > "Can spurious interrupts occur in the LPC200?",
> > 
> > Your answer is:
> > 
> > "Yes, spurious interrupts can occur in any ARM7 device that has 
> implemented 
> > the ARM Primecell Vectored Interrupt Controller (VIC)."
> > 
> > I tried looking for a reference to this in the ARM site but cannot 
> find any.
> > 
> > A search on "spurious" at the ARM web site yields 11 hits but 
> these appear 
> > not relevant to the VIC and spurious interrupt problem with the 
> ARM design 
> > that you seem to allude us to.
> > 
> > I also did a brief search for information on the web relating to 
> spurious 
> > interrupts, and all the examples seem to point to LPC one way or 
> another.
> > 
> > A spurious interrupt is a hardware interrupt which is generated by 
> system 
> > errors (http://www.answers.com/topic/interrupt-1), and systems 
> with 
> > spurious interrupts in general do not meet compliance requirements.
> > 
> > Please clarify:
> > 
> > 1/  Is this spurious interrupt problem an error in LPC 
> implementation of 
> > VIC or is it an error in ARM Primecell VIC specifications itself?
> > 
> > 2/  Can you tell us if there are any other ARM cores with VIC that 
> also 
> > suffer from spurious interrupts problem that the LPC suffers from?
> > 
> > Kind regards,
> > 
> > Jaya
> > 
> > PS:  I realise there has been discussion previously on spurious 
> interrupts, 
> > but none seem to throw any light on whether this is a problem 
> specific to 
> > LPC or it has to do with with ARM VIC design itself.
> > 
> > --- In lpc2000@yahoogroups.com, "philips_apps" <philips_apps@> 
> wrote:
> >  >
> >  > Hi,
> >  >
> >  > have a look at the FAQ here:
> >  >
> >  > http://www.standardics.philips.com/support/faq/microcontrollers/
> >  >
> >  > I also added a link in the link section named
> >  > "Philips FAQ for LPC2000 devices"
> >  >
> >  > Regards, Robert
> > 
> > Send instant messages to your online friends 
> http://au.messenger.yahoo.com
> >
>