Lpc2000

Hi

I come from the 8051 world and have some questions.

As i understand from the docs :

When i need interupt routines for 3 peripherals :

If i use vectored ISR's each peripheral will have its own isr where i clear
the irq request bits (if needed to do manually)
With vectored ISRs i can decide the priority by assigning the slot number.


If i use FIQ i will only need one ISR that contains code to check wich one
of the \ufffdperipherals did cause the interrupt.
My decision logic to test IRQ bits will decide on the priority.
The same way of dealing with the request bits when using the non vectored
way.(but has some more cpu overhead in restoring
registers ).


Did i interprete this correct ?

What happens if multiple IRQ's are set  and i only handle and clear one in
the FIQ routine ?

Will there still be gain in terms of latency between FIQ with multiple IRQ's
and Vectored ISR's ?

Thanks for helping.

Johan