Lpc2000

"Fast Interrupt reQuest (FIQ) requests have the highest priority. If more than one request is assigned to FIQ, the VIC ORs the requests to produce the FIQ signal to the ARM processor. The fastest possible FIQ latency is achieved when only one request is classified as FIQ, because then the FIQ service routine can simply start dealing with that device. But if more than one request is assigned to the FIQ class, the FIQ service routine can read a word from the VIC that identifies which FIQ source(s) is (are) requesting an interrupt."
  Above statement in the user manual of LPC213x clearly states that you should assign only one interrupt to the FIQ. Obviously you are assigning an interrupt to FIQ, as you want it to be of the highest priority and that it should be serviced as quickly as possible. So it is advisable to assign only one interrupt to the FIQ. If you are using Keil, the name of the interrupt you are assigning as FIQ should bear the name FIQ_HANDLER, as in:
void FIQ_HANDLER(void) __fiq
{
 unsigned long temp = (interrupt register);
 eg. temp = T0IR; // for timer0
 T0IR=temp; // this clears the interrupt
 switch(temp)
 {
  case x:
  bla..bla
  break;
    case y:
  bla..bla
  break;
 }
 VICVectAddr=0; // compulsory step, though the value put into VICVectAddr can be anything.
}
You can assign other two interrupts to irq (as you mentioned you are using three interrupts).
IRQs can have any name as in:
void interrupt_name(void) __irq
{
 unsigned long temp = (interrupt register);
 eg. temp = T1IR; // for timer1
 T1IR=temp; // this clears the interrupt
 switch(temp)
 {
  case x:
  bla..bla
  break;
    case y:
  bla..bla
  break;
 }
 VICVectAddr=0; // compulsory step, though the value put into VICVectAddr can be anything.
}
  In IRQs, the VICVectCntlx register determines the priority of the interrupt.
Lower the value of 'x', higher the priority. Assigning interrupt should be done as follows:
  /* assigning peripheral1 interrupt*/
VICVectAddr0=(UL*) interrupt_name;
VICVectCntl0=peripheral_cntl_no;
VICIntSelect=(fiq or irq);
VICIntEnable=peripheral_no;
   
  /* assigning peripheral2 interrupt*/
VICVectAddr1=(UL*) interrupt_name;
VICVectCntl1=peripheral_cntl_no;
VICIntSelect=(fiq or irq);
VICIntEnable=peripheral_no;
   
  As far as I know, 'x', as in VICVectAddrx and VICVectCntlx, should be same for any one peripheral initialisation.
   
  Jack.

Sagaert Johan <sagaert.j@...> wrote:
  Hi

I come from the 8051 world and have some questions.

As i understand from the docs :

When i need interupt routines for 3 peripherals :

If i use vectored ISR's each peripheral will have its own isr where i clear
the irq request bits (if needed to do manually)
With vectored ISRs i can decide the priority by assigning the slot number.


If i use FIQ i will only need one ISR that contains code to check wich one
of the £peripherals did cause the interrupt.
My decision logic to test IRQ bits will decide on the priority.
The same way of dealing with the request bits when using the non vectored
way.(but has some more cpu overhead in restoring
registers ).


Did i interprete this correct ?

What happens if multiple IRQ's are set  and i only handle and clear one in
the FIQ routine ?

Will there still be gain in terms of latency between FIQ with multiple IRQ's
and Vectored ISR's ?

Thanks for helping.

Johan






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