Lpc2000

--- In lpc2000@yahoogroups.com, "roger_lynx" <roger_lynx@...> wrote:

> 
> The question is, since the pipeline is three-staged, at which point
> the interrupt (IRQ/IFQ) is being sampled after fetch, decode or
> execute cycle? I would imply int. sampling happens after execute.
> Would someone clarify this ARM statement, please?
> Thanks.
> 
>

From http://www.arm.com/support/faqip/3678.html :

What happens if an interrupt occurs as it is being enabled?

Applies to: ARM7TDMI

Interrupts are enabled by clearing the I (for IRQ) or F (for FIQ)
flags in the CPSR with an MSR instruction. If an interrupt occurs as
it is being enabled, the instruction following the MSR instruction
will still be executed.

The reason is that the new flags are only available to the control
logic at the end of the execution stage of the MSR instruction. 
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
The next instruction will have already been decoded and enters the
execution stage of the instruction pipeline just as the flags are
being changed.