Lpc2000

Hi,

I have seen a similar issue before on another ARM derive that turned
out not to be a bug rather an alignment problem. What is the address
used in R1 (STRH R1,[R2]) when the issue occurs?

Check out this FAQ from ARM

http://www.arm.com/support/faqip/3661.html

In particular it says: "The result of all half word loads or stores
(issued as ARM or Thumb instructions) with a non-halfword aligned
address will be unpredictable"

Happy hunting,
Ken





--- In lpc2000@yahoogroups.com, Jayasooriah <jayasooriah@...> wrote:
>
> Hi Peter,
> 
> Your problem is interesting.
> 
> I lived through a few halfword bugs similar to yours and the source
in all 
> of these cases turned out to be either software or hardware
(interconnect) 
> but, not on-chip as you suspect.
> 
> I am assuming you have checked out that binary coding is okay and so 
> on.  It does not look like this is your problem from the symptoms you 
> describe -- one in ten characters being trashed.
> 
> My bet is that your problem going away when you replace the
instructions is 
> a side effect of your change rather than the cause.  I do not know
enough 
> about your project and thus have no idea what is involved in
tracking this 
> down to its source, but I think it is doable.
> 
> I would be interested in tracking it down if you are.  If not now,
at least 
> save the "problem" snapshot so that you can revisit it later.
> 
> Jaya
> 
> At 20:52 29/03/2006, you wrote:
> >Message: 25
> >    Date: Wed, 29 Mar 2006 19:44:38 +1000
> >    From: Peter Jakacki <peterjak@...>
> >Subject: Re: Re: ARM halfword bugs?
> ...
> >I have been having a sneaking suspicion that there is a bug elsewhere
> >(silicon?) when performing halfword accesses in ARM mode, that's what
> >the original post was about, not any difficulty with assembler.
> 
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