Lpc2000

Another way to generate non uart style serail data streams is to use a
timer and a compare unit.

This makes a hardware assisted bit bang type system. You program the
compare module to put out a high or low as required, then make it
generate an interrupt. In the isr you set the same compare module to
drive the next bit.

The benefit of using the compare module is that the edges are output
with perfect timing and you have quite a while to setup the next bit.
Unlike classic bit bang you can easily do other things at the same
time and it is nohwere near as compute intensive.

If you can dedicate a whole timer then you can get the compare to
reset the timer so you do not have to keep calculating a new time for
the compare unit.

If you want higher data rates then this can be done by allocating the
timer you are using to the FIQ and making use of the special FIQ
registers (so you do not have the overhead of stacking and unstaking
the used registers).

This techniquie is very useful on chips like the LPCs which are pretty
fast and have a low interrupt latency and can have VERY short isr
routines.