Lpc2000

This is the Atmel document that I used while I was
writing my JTAG based debugger for the LPC chips:
http://www.atmel.com/dyn/resources/prod_documents/doc2668.pdf

It was page 15 of this document where I saw the
reference to the NOP after the LD instruction (the
document is using a LDR instruction but I was using a
LDM instruction) to put the instruction in the decode
stage before the restart.  I also saw this mentioned
in at least one other part of the document as well
(page 18 with the full-speed STMIA).  I didn't do this
when I first wrote my memory reading code and I just
got gibberish back.  Once I added it, everything
started to work as I expected.

You mentioned in your original e-mail that you end the
memory load with the following 2 JTAG commands:
RESTART
INTEST

Do you also read the DSR ICE register to determine if
the core is back in the halted state or know that you
are just waiting long enough for the full-speed memory
access to occur?  I have also found that the RESTART
command switches the TAP back to scan chain 0.  What
happens if you insert a SCAN_N (chain 2) command
between the RESTART and INTEST commands?  The
functionality of scan chain 0 will definitely be
different between various chip vendors.


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