Lpc2000

Dear Brendan,

Please refrain from ask me anything if you do not need my help.

I do not wish to engage with you on this or any other topic.

Kind regards,

Jaya

--- In lpc2000@yahoogroups.com, "brendanmurphy37"
<brendanmurphy37@...> wrote:
>
> 
> Jaya,
> 
> I don't have any needs, nor do I need your help.
> 
> You made the following statement:
> 
> "It is because the watchdog timer on LPC is not wired to the Reset
> interrupt priority level of ARM7"
> 
> This contradicts information in the User Manuals, where it is stated 
> that the watchdog generates a reset.
> 
> Furthermore, there is no such thing as a "reset interrupt priority 
> level". A reset is a type of exception (as is an IRQ or FIR 
> interrupt). Resets have a higher priority than interrupts (and all 
> other exceptions, such as data aborts etc.).
> 
> See the ARM ARM for details.
> 
> All I'm asking is that if you have information to the contrary, 
> please share it rather than making incorrect statements and vague 
> claims about problems.
> 
> Best wishes
> Brendan