Lpc2000

At 08:29 AM 4/29/2006 +0000, jayasooriah wrote:
>Just so that others can see the kind of differences we are talking
>about, here is an excerpt of OKI user manual for 674001/675001 series:
>
><quote>
>
>6.2 Reset Types
>
>6.2.1 External Reset Input
>Driving the RESET_N pin at Low level for a pulse width at least 20
>clock cycles triggers a reset. When first applying the power or waking
>the LSI from STANDBY mode, however, increase the pulse width to at
>least 10 ms to allow the crystal oscillator sufficient time to stabilize.
>
>This type of reset leaves 0x0000 in the WDSTAT register.
>
>6.2.2 Watchdog Timer Overflow
>Setting the ITM and OFINTMODE bits in the watchdog time base counter
>control (WDTBCON) register to "0" and "1," respectively, causes
>watchdog timer overflow to trigger a system reset.
>
>This type of reset leaves 0x0001 in the WDSTAT register.
>
>This type also leaves the following LSI settings unchanged: I/O port
>direction (input/output), I/O port function (primary/secondary), I/O
>port output levels, and the oscillation stabilization interval
>specified in the clock wait (CKWT) register.
>
></quote>
>
>The designers have thought through what one uses the watchdog for and
>chose not to lump watchdog reset with the system reset as it appears
>to be for LPC.  Clearly there is no comparison.

So the difference would be
         - Leaves a different signature behind
         - Leaves the I/O in the state it was, quite possibly increasing 
the latency to a known good state.

The LPC does the first as well,  The second it does differently.  Better as 
far as I'm concerned.  However both are reasonably easily dealt with.  Only 
when running close to the edge would that be a deciding factor in choosing 
one over the other.

Not all processors distinguish between reset sources.

Robert


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