Lpc2000

Thanks to Robert Teufel for providing me with the following information.
I wish the support from other chip manufacturers could be this good.

The problem is tied to a very small time window within each clock
period. If a transition of the reset comes exactly during this time some
Flash configuration bytes do not get transferred. As a result, reading
the Flash though possible, uses a wrong configuration and usually it
reads all FF, however it could also read partially correct values as the
values transferred into the flash configuration bytes are undefined.



You can reduce the likelihood by using the slowest external clock
possible (less clocks during reset and so less time windows for the
issue to occur). So if you use 16 MHz today, try 12 MHz or even 10 MHz
if it fits your needs.  The only reliable work around is to apply a
second reset after the specified time in the Errata Sheet.

In approx. 6 weeks we should be able to provide sufficient quantities of
the LPC2129/00 which still has all the Erratas except the startup
problems.

Best regards, Robert Teufel
Software Development Manager




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