Lpc2000

Howdy,

> If you mean that 14.7Mhz * 1 is less than 156 Mhz, you're
> correct.  But so is 14.7Mhz * 4!  How are you supposed to
> get to 156Mhz if the multiplier cannot be greater than 6
> (see above)?  14.7Mhz * 1 is in the range of 10Mhz to 60Mhz.

There is a prescaler !

Look at PLLCFG register.
If you for example are after 14.7 MHz * 4 = 58.8 MHz,
then you would set the Multiplier(M) to 4, and the presaler (P)
could for example be 2 - thus :
Fcco = Fosc * M * 2 * P = 14.7 * 4 * 2 * 2 = 235.2 MHz.
cclk = Fosc * M  = 58.8 MHz.

If you now would want the M value to be only 1, then P would have
to be 4 times higher, ie. 8 - thus :
Fcco = Fosc * M * 2 * P = 14.7 * 1 * 8 * 2 = 235.2 MHz.
But cclk now is :
14.7 MHz * M = 14.7 MHz.

It sounds like the way you have it now, your PLL is incorrectly
programmed, the CCO is not capable of that low frequency, thus
the capture in range is not possible, _thus_ the PLL doesn't/can't lock.
The ref manual specifically states that you will yield unreliable operation.

Try setting the P and M values properly, and it should work properly then.
You need to change the "mov R1, # 0x24" instruction to change the prescaler
("divider") value.
For example, 0x25 sets P to 2 instead of etc.

-- Kris