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Message

Re: PLL Issues (was Help: Rowley CrossStudio & Wiggler Problem)

2004-04-18 by nw_mcu

--- In lpc2000@yahoogroups.com, Robert Adsett <subscriptions@a...> 
wrote:
> At 09:01 PM 4/18/04 +0000, you wrote:
> >PLLCFG = 0x44 (P=2, M=4): 231ns (Should be 59Mhz but is 73.5Mhz?)
> >PLLCFG = 0x23 (P=1, M=4): 231ns (as above)
> 
> How do you figure 231ns is a 73.5MHz clock?

If you do the math on the numbers I posted they are all 17 clock 
cycles--i.e. a 14.7Mhz clock is 68ns * 17 = 1156ns and 231ns/17 = 
73.5Mhz.

I've further confirmed the numbers by measuring the Timer0 period 
with a scope.  I've also confirmed the crystal circuit is always 
running at 14.7mhz.  I admit this seems REALLY strange!  Can anyone 
else reproduce these results?  Are lots of people running their 
LPC210X's at 5X instead of 4X and not realizing it?  Seems unlikely 
but I've double checked the measurements I've posted and they're 
accurate.  

The only thing I can think of is I somehow got a 2106 with bad PLL 
logic and/or damaged mine by using a too low Fcco?  Both seem pretty 
unlikely, however.

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