Lpc2000

At 12:04 AM 4/19/04 +0000, you wrote:
>--- In lpc2000@yahoogroups.com, "nw_mcu" <nw_mcu@y...> wrote:
>
>OK, I've now confirmed the PLL problem! With my 2106, I get the
>following results:

I thought I'd repeat the calculation for the rest of your results.


>PLL OFF: 1150ns (14.7Mhz)
>PLLCFG = 0x61 (P=3, M=1): 577ns (should be 14.7Mhz but is 29Mhz)
>PLLCFG = 0x21 (P=1, M=1): 577ns (as above)

I get Fcco of 235.2 MHz (in range), and cclk of 29.4 MHz

>PLLCFG = 0x42 (P=2, M=2): 384ns (Should be 29.4Mhz but is 44Mhz)

Fcco = 352.8 MHz (out of range), cclk 44.1 MHz

>PLLCFG = 0x43 (P=2, M=3): 288ns (Should be 44Mhz but is 59Mhz)

Fcco = 470.4 MHz (out of range), cclk = 58.8 MHz

>PLLCFG = 0x44 (P=2, M=4): 231ns (Should be 59Mhz but is 73.5Mhz)

Fcco = 588 MHz (way out of range), cclk = 73.5 MHz

>PLLCFG = 0x24 (P=1, M=4): 231ns (as above)

Fcco = 294 MHz (out of range), cclk = 73.5 MHz

Apparently there is a fair amount of margin in the PLL specs since it still 
seems to work even when Fcco is >2x the max.  Of course there's always the 
peripheral side effects to worry about.

However, the expected clock frequency matches the measured frequency in all 
cases.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III