Lpc2000

Hi everybody,
We are trying to work with LPC2104 & Keil uVision3.

If you take LPC2104 user's manual (2 oct 2003) you can read:
"If user's code is runing from the on-chip RAM and an aplication
uses 
interrupts, interrupt vectors must be re-mapped to flash
address 0x0." (from page 70, VIC usage notes)

BUT, you can also read:
"The user should either disable interrupts, or ensure that user 
interrupt vectors are active in RAM and that the interrupt handlers 
reside in RAM, before making a flash erase/write IAP call." (from 
page 180, Interrupts during IAP)

What we don't understand is the expression "ensure that user 
interrupt vectors are active in RAM". Active in RAM? We thought all 
interrupts & exceptions must be active in 0x0 and above (i.e., flash).

BTW, can we manage to hace two APPs in flash with diferent interrupt 
vector tables?

Thanks a lot in advance.

-.-WOLFISH-.-