Lpc2000

more_effective wrote:
> Hi everybody,
> We are trying to work with LPC2104 & Keil uVision3.
> 
> If you take LPC2104 user's manual (2 oct 2003) you can read:
> "If user's code is runing from the on-chip RAM and an aplication
> uses 
> interrupts, interrupt vectors must be re-mapped to flash
> address 0x0." (from page 70, VIC usage notes)
> 
> BUT, you can also read:
> "The user should either disable interrupts, or ensure that user 
> interrupt vectors are active in RAM and that the interrupt handlers 
> reside in RAM, before making a flash erase/write IAP call." (from 
> page 180, Interrupts during IAP)
> 
> What we don't understand is the expression "ensure that user 
> interrupt vectors are active in RAM". Active in RAM? We thought all 
> interrupts & exceptions must be active in 0x0 and above (i.e., flash).

Address 0 can appear in one of four places: the base of user flash, the 
base of user RAM, in external memory (for parts that support this) or 
somewhere in the Philips bootloader.  You have to put your vectors in 
one of the three user locations, then configure the remapping 
appropriately via the MEMMAP register.

If you're going to call IAP flash erase/write routines with interrupts 
enabled, you would have to have the vectors and the routines in RAM (or 
external memory) to ensure no access to the flash during the 
erase/program operation.

> BTW, can we manage to hace two APPs in flash with diferent interrupt 
> vector tables?

Probably the best way to accomplish this would be to have the vectors at 
the base of user RAM, then simply swap them in and out to match the 
application currently running.

Ryan