At 07:44 PM 5/29/04 +0000, you wrote:
>It's a difficult sentence, I admit. What I wanted to say is that I
>used the Rx transceiver on the Kickstart Board (instead of the
>MAX202 on my board) to ensure that the Rx signal at the LPC2106 is
>really clean (I have read a lot about bad decoupling etc. at the
>transceivers leading to unreliability).
Or it may just mean I was up too late :)
>Of course I was testing previously directly with my board which uses
>a 5V MAX202 transceiver and with this test I wanted to see whether
>there was a difference using a 3V transceiver and also a known good
>RX path.
>
>In fact the ISP utility is communicating with the Kickstart board
>and my board is simply listening in to the data received by the
>kickstart board. It responds and I compared its responses with those
>from the Kicksrat board. During an upload to the kick start board my
>board receives the same info and responds - the upload is successful
>since the responses seen at the ISP utility are from the Kickstart
>board which works perfectly. I monitor the responses from my board,
>which abruptly stop somewhere during the process.
>
>This means that I am definitely sure that it's not a tranceiver
>problem.
I don't share your certainty here. Let me sketch out a case where your
setup could fail even when all the components work. Each line represents a
moment in time. If you line up the '|'s you should see a table of events
in time during programming. This is just a rough sketch and I've certainly
left out details but it captures what I'd be worried about.
PC |
Kickstart | Your
Board | Monitor
... |
| |
1 Send Write data to
ram | |
|
2 | Receives
Data | Receives Data |
3 | Returns CMD_SUCCESS | Returns
CMD_SUCCESS |
4 Receives
CMD_SUCCESS | |
| Receives CMD_SUCCESS
5 Send Copy RAM to
Flash | |
|
6 | Starts copy RAM to
Flash | Starts copy RAM to Flash |
7 |
| Finishes copy RAM to Flash |
8 | Finishes copy RAM to
Flash | Sends CMD_SUCCESS |
9 | Sends
CMD_SUCCESS | |
Receives Sends CMD_SUCCESS
10 Receives
CMD_SUCCESS | |
|
11 Send Write data to
ram | |
|
..... Repeat multiple times
12 Send Write data to
ram | |
|
13 | Receives
Data | Receives Data |
14 | Returns
CMD_SUCCESS | Returns CMD_SUCCESS |
15 Receives
CMD_SUCCESS | |
| Receives CMD_SUCCESS
16 Send Copy RAM to
Flash | |
|
17 | Starts copy RAM to
Flash | Starts copy RAM to Flash | Starts copy RAM to Flash
18 | Finishes copy RAM to
Flash | |
19 | Sends
CMD_SUCCESS | |
20 Receives
CMD_SUCCESS | |
|
21 Send Write data to
ram | |
|
22 | Receives
Data | EEEK!! |
At line 22 (where I've put EEEK!!) your board receives a command it's
simply not ready for. It's not clear what will happen at this point but I
doubt that it's good. In fact I suspect it will leave the micro very
confused and it's possible it will abort the program cycle it is in. It
may at that point be so confused that it is effectively dead until it's
reset, there appears to be no documentation that hints at any sort of
recovery or error detecting strategy. I also suspect that the probability
of this happening approaches unity as you program more and more lines.
Robert
" 'Freedom' has no meaning of itself. There are always restrictions,
be they legal, genetic, or physical. If you don't believe me, try to
chew a radio signal. "
Kelvin Throop, IIIMessage
Re: [lpc2000] Re: ISP (explaination of difficult sentence)
2004-05-29 by Robert Adsett
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