Lpc2000

hodgejackiehank wrote:

> As soon as I write a single character to the THRE, Transmit holding
> register empty flag in U1LSR is cleared. Either the FIFO is not
> enabled or is set to '1', or this is the normal operation (after all,
> the FIFO is not **empty**).
> 
> In the latter case how do you know if there is still space in the FIFO
> to write data?
> 
> BTW, while trying to resove this problem I came accross the following
> comment in the control register descriptions:
> 
> 00: trigger level 0 (default='h1)
> 01: trigger level 1 (default='h4)
> 10: trigger level 2 (default='h8)
> 11: trigger level 3 (default='he)
> These two bits determine how many receiver UART1 FIFO characters must
> be written
> before an interrupt is activated. The four trigger levels are defined
> by the user at
> compilation allowing the user to tune the trigger levels to the FIFO
> depths chosen.
> 0
> 
> 
> 
> What exactly does it mean by defined at compile time? Perhaps if I
> knew where these levels were configured I would find the answer to my
> Tx FIFO problem ?!
> 
> 
> 
> 

I also stumbled across this description. Obviously, this is a copy-and-paste 
from the description of the '550-UART IP-Core. So, 'compile time' means the time 
of the building of the chip, when all the hardware descriptions (in VHDL, 
Verilog or whatever) are translated and mapped onto the target technology and 
'user' in this case is/are the chip designer(s).
IIRC, somewhere in the user manual is explicitely said that the FIFO holds 16 
byte with possible trigger levels being 1, 4, 8 or 14.

Regards,
Jens