Lpc2000

--- roger_lynx <roger_lynx@...> wrote:

> ...... 
> 
> Does this snippet look okay (for IRQ ints)?
> 
>           NOP                       	
>           LDR PC, [PC, #-0xFF0] <---- what happens
> here?
>           LDR PC, FIQ_Addr
>                
> Undefined_Addr: .word Undefined_Handler
> SWI_Addr:       .word SWI_Handler
> Prefetch_Addr:  .word Prefetch_Handler
> Abort_Addr:     .word Abort_Handler
> FIQ_Addr:       .word FIQ_Handler
> 
> Happy SW trails!
> 
> --roger
> 
LDR PC, [PC, #-0xFF0] instruction is loacted at
0x00000018, which means the PC would have advanced to
0x00000020 this value offset -0x0FF0 would address the
location at 0xFFFF F030, which is the address of VIC
Vector Address Register. (Given in the User Manual)
You should have your IRQHandler for UART0-THRE 
Address loaded into the VICVADDRx (x between 0 to 15)
and correspondingly the VICCNTLx (corresponding to the
VICVADDR - x) should be set to 0x26 (bit 5 = 1 
indicates this Vectored IRQ slot is enabled, bit 4:0
has the value of 0b00110 indicates UART0 is enabled
for this slot). This is explained in Philips AN10254.

The instruction at 0x18 can handle all the interrupts
that are enabled in VIC, by automatically jumping to
the IRQ handler of the specific interrupt that took
place.
Hope this clarification (is correct!) and it helps
you.
Cia
Mathew 


		
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