Lpc2000

Looks like you found a mistake in my header files.  The bit definitions
for the Fifo Control Register should be as follows:

// FIFO Control Register bit definitions
#define UFCR_FIFO_ENABLE    (1 << 0)    // FIFO Enable
#define UFCR_RX_FIFO_RESET  (1 << 1)    // Reset Receive FIFO
#define UFCR_TX_FIFO_RESET  (1 << 2)    // Reset Transmit FIFO
#define UFCR_FIFO_TRIG1     (0 << 6)    // Trigger @ 1 character in FIFO
#define UFCR_FIFO_TRIG4     (1 << 6)    // Trigger @ 4 characters in FIFO
#define UFCR_FIFO_TRIG8     (2 << 6)    // Trigger @ 8 characters in FIFO
#define UFCR_FIFO_TRIG14    (3 << 6)    // Trigger @ 14 characters in FIFO

I will correct the header file and repost the example code.

-Bill



On Fri, 30 Jul 2004 14:32:58 -0000, Leighton Rowe wrote:

--- In lpc2000@yahoogroups.com, "Bill Knight" <BillK@t...> wrote:
> You might want to check my contribution to the files section on 
Yahoo.
> The descriptively titled 'UT040322A.zip', contains an interrupt or
> polled (your choice) UART driver, non-interrupt system timer, and a
> blinky lights program.  It may be of help to you.
> 
> Regards
> -Bill Knight
> the ARM Patch

Hey Bill,

I took a close look at the 'UT040322A.zip' files and I noticed 
something in the UART initializer ("uart0Init" in uart.c) that I 
need your clarification on.

;void uart0Init(uint16_t baud, uint8_t mode, uint8_t fmode)
;{
;......
;......
;  // set the number of characters and other
;  // user specified operating parameters
;  U0LCR = (mode & ~ULCR_DLAB_ENABLE);
;  U0FCR = fmode;

There are defines for bits 4 & 5 of fmode that I think corresponds 
to TxFIFOs (interpreting the header files). But I thought writing 
1's to the UART FCR [5:3] shouldn't be done (stated in the lpc21xx 
manual)...unless u really know what u are doing. I can't find any 
documentation in the manual for setting TxFIFO levels but that piece 
of code seems to suggest otherwise. Could u explain what the 
Reserved bits ( 3, 4 & 5) in U0FCR [5:3] are for? 

Thanks. 
Leighton







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