Lpc2000

At 12:39 AM 9/18/04 +0000, you wrote:
>This solution will cure problem only if an ISR is doing a write to
>the WD register space.

On the other hand the PLL, which uses the same feed sequence,  explicitly 
states in its documentation that the two write must be on consecutive VPB 
bus cycles.  Perhaps the Watchdog documentation is wrong?

It might be worth a quick try to see if it had any effect.  If it did then 
it would be time to beg for clarification from Philips.

Robert

" 'Freedom' has no meaning of itself.  There are always restrictions,
be they legal, genetic, or physical.  If you don't believe me, try to
chew a radio signal. "

                         Kelvin Throop, III