Lpc2000

Make sure you are in thumb mode before calling any IAP code (as it is
implemented in thumb).
 
 
Hugh @ http://www.ashling.com/support/lpc2000/

-----Original Message-----
From: helmutbitter [mailto:helmut.bitter@...] 
Sent: 04 October 2004 11:54
To: lpc2000@yahoogroups.com
Subject: [lpc2000] Re: IAP command problems



--- In lpc2000@yahoogroups.com, "koerner_stefan" <koerner.stefan@a...>
wrote:
> Could anyone help me to run the IAP commands on KEIL MCB2100 
> (LPC2129)?
> 
> I am working with the ARM RVDS tools (& RV ICE) and tried to run a 
> small sample calling the IAP commands (program runs from iRAM).
> 
> Most time I get a "memory access violation" several seconds after 
> calling the IAP commands.
> Sometimes the first IAP command (code 50) runs ok but I did never saw 
> a guilty write command. I tried it also with cclk = 12MHz. Do I have 
> to do additional initialisation?
> I have reserved 16 bytes on top of Stack.
> 
> best regards
> Stefan
> 
> This is my source
> 
> ...

I have some problems with the IAP as well.
After upgrading to version 1.63 bootloader (one is a LPC 2124 the
other a LPC 2129) the behavior is predictable but not what should happen.
I do 4 steps: 1. prepare 2. erase 3. prepare 4. coppy RAM to flash.
Steps 1. to 3. show as Status Code CMD_SUCCESS but definetly erase
does not work. Step 4. gives back 9
SECTOR_NOT_PREPARED_FOR_WRITE_OPERATION.

Any help would be appreciated.

Thanks 

Helmut Bitter 

Part of my source follows:

static void 
flash_schreiben (unsigned int *puffer)
{
  iap_entry=(iap) iap_location;

  /* Stop A/D Wandler */
  ADCR = 0x01;

  /* Disable Interrupts */
  __ARMLIB_disableIRQ(); 

  /* Disable FIQ */
  __ARMLIB_disableFIQ();

  PLLCON = 0; // disable PLL, cclk = Fosc
  PLLFEED=0xaa;
  PLLFEED=0x55;
  while ((PLLSTAT & 0x300) ==0x300 ); // warten bis PLL nicht mehr
Clock Source

  /* Stopp MAM */
  MAMCR = 0;

  command[0]=55; // Boot Code Version
  iap_entry (command,result);

  /* zuerst Sector löschen */
  /* ein "Prepare" Kommando ausführen */
  command[0]=50; // Prepare Sector
  command[1]=sector; // Start Sector
  command[2]=sector; // End Sector
  iap_entry (command,result);
  if (result[0]!=0)
  {
    // Fehlermeldung
      delay (117000);
      IO1SET=0x00010000;
      IOSET=0x02000000;
      delay (117000);
      IO1CLR=0x00010000;
      IOCLR=0x02000000;
  }
  /* "Erase" Kommando geben */
  command[0]=52;    // Erase
  command[1]=sector;    // Start Sector
  command[2]=sector;    // End Sector
  command[3]=10000; // Takt Frequenz in KHz
  iap_entry (command,result);
  if (result[0]!=0)
  {
    // Fehlermeldung
    for (i=2;i;--i)
    {
      delay (117000);
      IO1SET=0x00010000;
      IOSET=0x02000000;
      delay (117000);
      IO1CLR=0x00010000;
      IOCLR=0x02000000;
    }
  }

  /* nun Copy RAM to Flash */
  /* dazu zuerst ein "Prepare" Kommando ausführen */
  command[0]=50; // Prepare Sector
  command[1]=sector; // Start Sector
  command[2]=sector; // End Sector
  iap_entry (command,result);
  if (result[0]!=0)
  {
    // Fehlermeldung
    for (i=3;i;--i)
    {
      delay (117000);
      IO1SET=0x00010000;
      IOSET=0x02000000;
      delay (117000);
      IO1CLR=0x00010000;
      IOCLR=0x02000000;
    }
  }

  /* jetzt das "Copy RAM to Flash" Kommando ausführen */
  command[0]=51;            // Copy RAM to Flash
  command[1]=sector_adr;    // Destination Flash address
  command[2]=(int)puffer;   // Source RAM address
  command[3]=512;           // Anzahl Bytes, die ins Flash geschrieben
werden sollen
  command[4]=10000;         // Taktfrequenz in KHz
  iap_entry (command,result);
  /* Fehlerauswertung nach dem Flashen */
  if (result[0]!=0)
  {
    // Fehlermeldung
    for (i=4;i;--i)
    {
      delay (117000);
      IO1SET=0x00010000;
      IOSET=0x02000000;
      delay (117000);
      IO1CLR=0x00010000;
      IOCLR=0x02000000;
    }
  }
  else
  {
    /* flashen war erfolgreich, deshalb 1x Summer und grüne LED an-
und ausschalten */
    delay (434000);
    IO1SET=0x00010000;
    IOSET=0x02000000;
    delay (434000);
    IO1CLR=0x00010000;
    IOCLR=0x02000000;
    delay (434000);
  }

  /* PLL wieder als Clock Source */
  PLLCON = 1; // enable PLL
  PLLCFG = 0x25; // M=6 and P=2 -> Cclk = 60 MHz bei 10 MHz Quarz
  PLLFEED = 0xAA; // PLL Feed Sequence
  PLLFEED = 0x55; // PLL Feed Sequence

  while (!(PLLSTAT & 0x400)); // wait for the PLL to be locked

  PLLCON = 3; // enable and connect PLL
  PLLFEED = 0xAA; // PLL Feed Sequence
  PLLFEED = 0x55; // PLL Feed Sequence

  /* MAM wieder freigeben */
  MAMCR = 0;
  MAMTIM = 0x03;
  MAMCR = 2;
  

  /* Enable Interrupts */
  __ARMLIB_enableIRQ(); 

  /* Enable FIQ */
  __ARMLIB_enableFIQ();

  /* Start A/D-Wandlung von ain0 ... ain3 im Burst Mode */
  ADCR = 0x00210D0F;
}
  









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