Lpc2000

This message was posted some months ago (early July):

--- In lpc2000@yahoogroups.com, h s <h7242004@y...> wrote:
> Has any one been able to successfully run all 4-compare channels of 
timer0 simultaneously (in the match interrupt mode, while the main 
timer0 is free running)? 
> The mode of operations could be such that one match channel is 
reloaded at a period rate. The other channels may be started and 
stopped as needed.  
>  
> I am losing match interrupts. 

I'm having exactly the same problem. MR0 is used to generate a system 
tick every 1ms and I periodically use MR1 and MR2 to generate 
interrupts every 26us and 52us respectively. Loading and starting of 
MR1 is synchronised to a capture input while loading and starting of 
MR2 is based on the program flow (MR1 and MR2 are used as a bit 
bashed serial port if you hadn't already guessed!). Multiple 
interrupt conditions can exist when the timer ISR is entered. A match 
is eventually missed on either MR0 or MR2. 

I've added debug code to store the TC value when the new match values 
are calculated and loaded. Every time the system stops working, 
examination of the debug variables show that TC value has advanced 
beyond the required match value, but no match interrupt seems to have 
been generated (and it's nowhere near a wrap either). Timer0 is set 
to increment every 1us and it generates the system's only FIQ. The 
time spent in any of the three associated interrupt routines is 
minimal - no longer than 4us, typically 2us. Any ideas?