Lpc2000

This may be, perhaps, a bit off topic.

I'm trying to make sense of the IRQ modle of the ARM core on the lpc2124.  My 
understanding of how this works is based on the ARM port to Linux, and the 
ARM refrence manual.  

I'm a bit confused.

On IRQ interrupt (not FIQ) the CPU switches to the ARM interrupt registers and 
branches to the irq vector currently installed.  

The ARM manual states that your ISR should do its thing, and to return back to 
the interrupted state execute "subs pc lr 4"  or something very close (I'm 
doing this from memory at the moment so the actual instruction may be a bit 
different).

However; in Linux this happens the following way;
entry.S has the __irq_svr handler, that calls do_IRQ, now do_IRQ sometime 
can / will re-enable interrupts.

Now how can another IRQ happen before returning back to the non-IRQ register?  
Wouldn't that mess things up if it one did?  

My other problem is that I cannot find that magic opcode ("subs pc lr 4") to 
return from the interrupt, is there another way to return the ARM processor 
registers to non-IRQ register set?  Or is this just an Linux-ism.

Sorry once again that this a bit off topic.  (It is an ARM question... ;)

Thanks,

--mgross