Our prototype LPC2292 boards only enable JTAG outputs when both the P1.26 pin (required in documentation) and the P0.14 (required for on-chip boot loader operation) are pulled low during reset. If P0.14 pin is left high during reset, P1.27 (TDO) becomes an input (weak pull up). If P0.14 is pulled low during reset, P1.27 is driven low as an output. We have a demo board with an LPC2294 that does not exhibit this dependence on the P0.14 line. We are using the Wiggler and ocdremote/gdb. This relationship is not mentioned in any documentation I have seen. Does anyone have any additional information that can help me understand our observations? Thanks Dave
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Problem getting into JTAG mode
2004-11-11 by David Roethig
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