Lpc2000

At 09:57 AM 11/23/03 +1100, you wrote:
>Hi Robert,
>
>Thanks for that, it's a strange one.
>Do you know if maybe NOPs are inserted in the pipe ?
>I can't figure it out.

I would expect that the VPB peripheral responsible is just asserting wait 
states.  Modifying the core to insert NOPs into the pipe would be a larger 
task and I don't see very many benefits.


>Also, do you know if we have faster access executing from RAM ?
>I assume the bus is the bottleneck anyway.

If it was limited by the speed of fetching instructions then I would expect 
a 1/3 - 2/3 duty cycle on the output.  I only get that for the default case 
with the MAM turned off and flash access set to the default 7 cycles.  Once 
the MAM is enabled it seems likely that the three instructions in the loop 
are maintained in the MAM's cache and so have no access delay.  There is 
asymmetry but I think the shape is dominated by the output peripheral.

>The VPB bottleneck has me completely stumped.

I suppose it might be the VPB but I suspect it's the actual I/O peripheral 
that's speed limited.

>I can't figure why it affects IO for starters anyway...... (or UART for that
>matter)
>Some more detective work might be needed :-)

The UART has me puzzled.  I'm going to do some more investigation and I've 
posted a question to Philips forum to see if there is some frequency 
limitation I've overlooked or is undocumented.

Robert Adsett


>All the best,
>Kris
>www.microbit.com.au
>
>
>----- Original Message -----
>From: "Robert Adsett" <radsett@...>
>To: <lpc2100@yahoogroups.com>
>Sent: Sunday, November 23, 2003 9:47 AM
>Subject: Re: [lpc2100] Simple test program - is now instruction pipeline/VPB
>question
>
>
> > At 05:07 AM 11/23/03 +1100, you wrote:
> > >The 2nd question is, what if I write at a slower rate to VPB ?
> > >Do I still need the fastest pclk for my I/O pins to update as fast as
> > >possible ?????
> > >(I can't trace :-)
> > >
> > >As an example, C code generating this sequence :
> > >.......
> > >STR     R4,[R7,#0]            P0.0 set to "1"
> > >MOV    R4,#1
> > >STR     R4,[R0,#0]            P0.0 set to "0"
> > >......
> > >
> > >Takes :
> > >1.6 uS (16 cclks) with pclk = 4 cclks
> > >1.0 uS (10 cclks) with pclk = 2 cclks
> > >0.8 uS (8 cclks)  with pclk = 1 cclks
> > >
> > >(that's what I measure here on HW)
> > >
> > >Is there anyone that can shed some light on this ?
> > >
> > >
> > >
> > >toggling P0.0 with pclk = cclk/4
> > >
> > >
> > >-- Kris
> > ><http://www.microbit.com.au>www.microbit.com.au
> > >
> >
> > I was going to play with bus optimization next anyway so I thought I'd
> > measure the results and pass them along.
> >
> > All of these with a 10MHz clock PLL'd to 60MHz.
> >
> > MAM Off
> > ASM optimized 1.06uS period ~740nS on ~330nS off
> > C  1.8uS period ~800ns on ~1uS off
> >
> > MAM on, Access to flash at recommended 3 cycles, VPB divider at default.
> > ASM optimized near square wave with 600nS period
> > C near square wave with 736nS period
> >
> > MAM on , Access to flash at recommended 3 cycles, , VPB divider to 1
> > ASM optimized 264nS period ~168nS off ~118nS on
> > C near square wave with 416nS period
> >
> > The (hand) optimized assembly loop used is
> >
> >          mov     r3, #256
> >          ldr     r2, .L67+32
> >          ldr     r4, .L67+36
> > .L64:
> >          str     r3, [r2, #0]
> >          str     r3, [r4, #0]
> >          b       .L64
> >
> > If the output is instruction rate limited then I would expect an output
> > with an approx 2/3 duty cycle.  That is only approached for the first
> > case.  For all other cases there is clearly some time taken up with I/O.
> >
> > Also clearly getting maximum throughput will depend on setting up the bus
> > 'correctly'.
> >
> > Setting the VPB divider to 1 in this configuration also seems to have an
> > effect on the UART.   I haven't figured that out yet but what should be
> > 9600 baud drops to about 9000 baud.
> >
> > Robert Adsett
> >
> >
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