Lpc2000

Hello All,

I want to use the SPI bus for communication between a LPC2129 and a 
FPGA. I think that I will decide to make the processor the 'Master'.

But I was wondering, suppose that I would use the LPC2129 as a Slave 
instead of a Master, how can I guarantee that the write buffer gets 
filled at the right moment. There is no buffer between the write buffer 
and the actual shift register, so the register needs to be written in 
the short interval between the transmission of the bytes (assuming a 
message with several bytes).

The problem is, if the LPC2129 is used as the Slave then the timing is 
determined by the Master at the other end. Isn't this getting tricky?

Regards,

-- 
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Aalt Lokhorst
Schut Geometrische Meettechniek bv
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E-mail: Lokhorst@...
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