Lpc2000

Looks like you found the cause. You just need to tell the CPU to flush its 
pipeline. In the ARM ARM book, it mentions that

"The overall result is that code which writes one or more instructions to 
memory and then executes them (know as self modifying code) cannot be 
executed reliably on ARM processors without special precautions..." and then

"Each implementation therefore defines a sequence of operations that can be 
used in the middle of a self-modifying code sequence to make it execute 
reliably. This sequence is called an Instruction Memory Barrier...."

So "all" you have to do is look thru the LPC2K datasheet and hope they 
describe what the IMB sequences are!!

Good luck,

At 07:05 AM 1/16/2005, sig5534 wrote:



>Same result.  Still not working.  I get the Prefetch Abort Except.
>
>When I trace it in the debugger I can see that it gets right to the
>call instruc:
>
>    LDR    PC,[R5,#0]
>
>And then it jumps to the Prefetch Abort Excep.
>
>R5 is loaded with 0x40000000 which is the right RAM area, and the
>debugger says the IAP_Test() routine is at that location.  I can see
>the code is there as well in the debugger source.
>
>Everything is right but the CPU is complaining about it's pipeline.
>Obviously executing code in flash ROM and then jumping to RAM is
>entirely different types of memory.  It's confusing the memory
>manager prefetch pipeline.
>
>There must be something I am missing.  Something else is apparently
>necessary to tell the CPU the next instruc is in RAM. Otherwise the
>CPU instruc fetch fails.  Why?
>
>Chris.
>
>
>
>
>
>
>
>Yahoo! Groups Links
>
>
>
>

// richard (This email is for mailing lists. To reach me directly, please 
use richard at imagecraft.com)