Lpc2000

From what I've seen, the self modifying code precautions in the ARMARM 
are mostly relevant to CPUs with caches. With caches, particularly 
with CPUs that have seperate caches for instructions and data. Clearly 
if you have an instruction cache that is different from the data cache 
you need to flush the caches to get the instructions to fetch 
properly.

The LPC21xx does not have caches, except for the MAM, so this is not 
an Ichache/Dcache issue.

I regularly use RAM-based code on ARM7s, but I achieve this by using 
the linker (GNU ld) to set up the addresses and my maincrt.s copies 
the RAM code from flash to RAM at start up. This is essentially what 
the .data thing will do too.
 
Some things that are worth considering:
1) Try turning off the MAM to eliminate this from the set of variable.

2) Are you using Thumb code? If so, perhaps the .data assignment is 
throwing away the thumb attributes.

3) A Prefetch Abort means that there is no memory available at the 
address you specify (like a data abort, but for instructions).

The code 

    LDR  PC,[R5,#0]

should be loading the pointer from this address (ie. R5 + #0 should be 
a 32-bit value that is the pointer to the code).

Check that the address actually contains the **pointer** to the code 
you want to execute and not the actual code itself.

Perhaps try

static const (*fnptr)(void) = IAP_Test;
 ...
 *fnptr();
 ...

which should put the pointer in the literal pool and generate 
different code.






 In lpc2000@yahoogroups.com, Richard <richard-lists@i...> wrote:
> Looks like you found the cause. You just need to tell the CPU to 
flush its 
> pipeline. In the ARM ARM book, it mentions that
> 
> "The overall result is that code which writes one or more 
instructions to 
> memory and then executes them (know as self modifying code) cannot 
be 
> executed reliably on ARM processors without special precautions..." 
and then
> 
> "Each implementation therefore defines a sequence of operations that 
can be 
> used in the middle of a self-modifying code sequence to make it 
execute 
> reliably. This sequence is called an Instruction Memory Barrier...."
> 
> So "all" you have to do is look thru the LPC2K datasheet and hope 
they 
> describe what the IMB sequences are!!
> 
> Good luck,
> 
> At 07:05 AM 1/16/2005, sig5534 wrote:
> 
> 
> 
> >Same result.  Still not working.  I get the Prefetch Abort Except.
> >
> >When I trace it in the debugger I can see that it gets right to the
> >call instruc:
> >
> >    LDR    PC,[R5,#0]
> >
> >And then it jumps to the Prefetch Abort Excep.
> >
> >R5 is loaded with 0x40000000 which is the right RAM area, and the
> >debugger says the IAP_Test() routine is at that location.  I can 
see
> >the code is there as well in the debugger source.
> >
> >Everything is right but the CPU is complaining about it's pipeline.
> >Obviously executing code in flash ROM and then jumping to RAM is
> >entirely different types of memory.  It's confusing the memory
> >manager prefetch pipeline.
> >
> >There must be something I am missing.  Something else is apparently
> >necessary to tell the CPU the next instruc is in RAM. Otherwise the
> >CPU instruc fetch fails.  Why?
> >
> >Chris.
> >
> >
> >
> >
> >
> >
> >
> >Yahoo! Groups Links
> >
> >
> >
> >
> 
> // richard (This email is for mailing lists. To reach me directly, 
please 
> use richard at imagecraft.com)