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Message

Re: 2138 Data Abort Loading SSP Reg

2005-01-26 by tkreyche

Dave,

I'm starting to think that there is an incompatibility between the TI 
spec and the 2138 on the receive timing. I tried both phases and they 
both sortof work but not quite perfectly. The ADC responds correctly 
to the transmit but the receive isn't read properly. The SPI specs 
from the two companies are written very differently...I need to go 
back and re-read.

Next I think I'll try the SPI port and see what happens. The specs 
for that seem to be lifted out of an earlier manual and the phase is 
not described the same way as it is for the SSP port. 

I had no such problems when I wired up and tested with the 8-bit 
micro (Rabbit 3000)...it worked perfectly.

Tom


--- In lpc2000@yahoogroups.com, "dsidlauskas1" <dsidlauskas@w...> 
wrote:
> 
> Tom,
> 
> Does your SSP clock phasing match the ADC?
> 
> Keil says the LPC213x problem will be fixed by the end of February.
> Also be aware that SSPCR0 and SSPDR should be defined in LPC213x as
> short * rather than char *.
> 
> Dave
>

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