Lpc2000

On Friday 04 February 2005 08:36, you wrote:
> --- In lpc2000@yahoogroups.com, "Tutors of ESAcademy"
>
> <esacademy@g...> wrote:
> > > Maybe someone can answer this detaily question.  In CANBTR the
> > > default values add up to a bit time of 15 time quanta (CAN
> >
> > clocks).
> >
> > > This is TSEG1 + TSEG2. BUT, reading the User Manual really
> >
> > carefully
> >
> > > it is clear the number is 16 time quanta.  Where is that one
>
> extra
>
> > > quanta?
> >
> > I have seen this on several CAN controllers. The first time quanta
>
> is
>
> > just always there, you can't configure it - so some sort of start-
> > time-quanta...
> >
> > Olaf
>
> Olaf,
> Yes that seems to be the case.  I wonder if it is part of the CAN
> standard (probably is).  In my mind it is connected with the re-sync
> functionality but perhaps it has nothing to do with it.  BTW, Thank
> you VERY much for the CAN source code.
> James
>

The TSEG1 + TSEG2 in the BTR don't add up to the full number because both of 
these are +1.  Then there's the sych seg which is fixed at one time quanta. 
Therefor the full bit period == (1)(TSEG1 value in BTR  + 1)+ (Tseg2 value in 
BTR + 1).

This register layout is not part of the CAN spec. The CAN spec concerns 
itself only with what goes on the wire, not how software interacts with the 
CAN controller.

NB though that some higher level protocols (protocols on top of CAN) will 
specify things like sampling points (ie. TSeg1 vs TSeg2)

CAN bit timing is a bit quirky, but it works well once understood.