Lpc2000

--- In lpc2000@yahoogroups.com, "embeddedjanitor" <manningc2@a...> 
wrote:
> 
> 
> > > 
> > > The TSEG1 + TSEG2 in the BTR don't add up to the full number 
> > because both of 
> > > these are +1.  Then there's the sych seg which is fixed at one 
> > time quanta. 
> > > Therefor the full bit period == (1)(TSEG1 value in BTR  + 1)+ 
> > (Tseg2 value in 
> > > BTR + 1).
> > > 
> > > This register layout is not part of the CAN spec. The CAN spec 
> > concerns 
> > > itself only with what goes on the wire, not how software 
interacts 
> > with the 
> > > CAN controller.
> > > 
> > > NB though that some higher level protocols (protocols on top 
of 
> > CAN) will 
> > > specify things like sampling points (ie. TSeg1 vs TSeg2)
> > > 
> > > CAN bit timing is a bit quirky, but it works well once 
understood.
> > 
> > Hi Robert,
> > My question was about the 1 time quanta "synch seg".  Is that 
part 
> > of the CAN spec and what is it for?
> > James
> 
> According to the CAN spec there are actually 4 parts to the bit 
> period. 
> * Sync seg: always 1 tq. Edges are expected here.
> * Prog seg: compensates for propagation delays.
> * Phase seg 1: Part of phase seg before sampling point.
> * Phase seg 2: Part of phase segment after sampling point
> 
> TSEG1 is a lumping of prop seg + phase seg 1. TSEG2 is just phase 
seg 
> 2.
> 
> If you really want to go deep-end this, read http://www.keil.
> com/dd/docs/datashts/silabs/boschcan_ug.pdf

Great!  Thanks for that clarification.
James