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Re: [lpc2000] Re: MAM and how to get the most from the LPC2106

2005-02-11 by k b shah (lascaux)

I think, you can look at user guide for PC2292/2294    

UM_LPC21XX_LPC22XX_2_FULLDATA.pdf

 on page 90 to 94 describe abour MAM and the control registers. the copy is provided here for reference... from the manual.
Memory Accelerator Module (MAM) 93 May 03, 2004

MAM CONFIGURATION

After reset the MAM defaults to the disabled state. Software can turn memory access acceleration on or off at any time. This

allows most of an application to be run at the highest possible performance, while certain functions can be run at a somewhat

slower but more predictable rate if more precise timing is required.

REGISTER DESCRIPTION

All registers, regardless of size, are on word address boundaries. Details of the registers appear in the description of each

function.

*Reset Value refers to the data stored in used bits only. It does not include reserved bits content.

Table 37: Summary of System Control Registers

Name Description Access

Reset

Value*

Address

MAM

MAMCR

Memory Accelerator Module Control Register. Determines the MAM

functional mode, that is, to what extent the MAM performance

enhancements are enabled. See Table 38.

R/W 0 0xE01FC000

MAMTIM

Memory Accelerator Module Timing control. Determines the number of

clocks used for Flash memory fetches (1 to 7 processor clocks).

R/W 0x07 0xE01FC004

Memory Accelerator Module (MAM) 94 May 03, 2004

Philips Semiconductors Preliminary User Manual

LPC2119/2129/2194/2292/2294 ARM-based Microcontroller

MAM Control Register (MAMCR - 0xE01FC000)

Two configuration bits select the three MAM operating modes, as shown in Table 38. Following Reset, MAM functions are

disabled. Changing the MAM operating mode causes the MAM to invalidate all of the holding latches, resulting in new reads of

Flash information as required.

MAM Timing Register (MAMTIM - 0xE01FC004)

The MAM Timing register determines how many cclk cycles are used to access the Flash memory. This allows tuning MAM timing

to match the processor operating frequency. Flash access times from 1 clock to 7 clocks are possible. Single clock Flash

accesses would essentially remove the MAM from timing calculations. In this case the MAM mode may be selected to optimize

power usage.

MAM USAGE NOTES

When changing MAM timing, the MAM must first be turned off by writing a zero to MAMCR. A new value may then be written to

MAMTIM. Finally, the MAM may be turned on again by writing a value (1 or 2) corresponding to the desired operating mode to

MAMCR.

For system clock slower than 20 MHz, MAMTIM can be 001. For system clock between 20 MHz and 40 MHz, Flash access time

is suggested to be 2 CCLKs, while in systems with system clock faster than 40 MHz, 3 CCLKs are proposed.

Table 38: MAM Control Register (MAMCR - 0xE01FC000)

MAMCR Function Description

Reset

Value

1:0

MAM mode

control

These bits determine the operating mode of the MAM as follows:

0 0 - MAM functions disabled.

0 1 - MAM functions partially enabled.

1 0 - MAM functions fully enabled.   use this to take full advantage 

1 1 - reserved

0

7:2 Reserved

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

Table 39: MAM Timing Register (MAMTIM - 0xE01FC004)

MAMTIM Function Description

Reset

Value

2:0

MAM Fetch

Cycle timing

These bits set the duration of MAM Flash fetch operations as follows:

0 0 0 = 0 - Reserved.

0 0 1 = 1 - MAM fetch cycles are 1 processor clock (cclk) in duration.

0 1 0 = 2 - MAM fetch cycles are 2 processor clocks (cclks) in duration.

0 1 1 = 3 - MAM fetch cycles are 3 processor clocks (cclks) in duration.

1 0 0 = 4 - MAM fetch cycles are 4 processor clocks (cclks) in duration.

1 0 1 = 5 - MAM fetch cycles are 5 processor clocks (cclks) in duration.

1 1 0 = 6 - MAM fetch cycles are 6 processor clocks (cclks) in duration.

1 1 1 = 7 - MAM fetch cycles are 7 processor clocks (cclks) in duration.

Warning: Improper setting of this value may result in incorrect operation of the device.

0x07

7:3 Reserved

Reserved, user software should not write ones to reserved bits. The value read from a

reserved bit is not defined.

NA

Philips Semiconductors Preliminary User Manual

LPC2119/2129/2194/2292/2294 ARM-based Microcontroller





k b shah

  ----- Original Message ----- 
  From: acetoel 
  To: lpc2000@yahoogroups.com 
  Sent: Friday, February 11, 2005 6:37 AM
  Subject: [lpc2000] Re: MAM and how to get the most from the LPC2106



  Also, now I'm using Thumb Mode, as I'm compiling with -mthumb. 
  To run it in ARM mode it should be -marm ?

  Thanks

  Kimi

  --- In lpc2000@yahoogroups.com, "acetoel" <acetoel@y...> wrote:
  > 
  > Hello
  > 
  > I would like to know how to get the most of the LPC in Speed and
  > Performance... Now I'm using a 10MHz crystal PLLed to 60MHZ for PCLK
  > and CCLK, and 240Mhz Fcco (what is this?).
  > But set MAM or other optimization parameter... well, how can I do it,
  > and which is the most powerful configuration (it doesn't care that the
  > MCU consumes more current, my supply is a 12V 7.4Ah Gel Battery)
  > 
  > Thanks
  > 
  > Kimi




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