Lpc2000

i was planning on accessing the ram via a state machine, where read and write cycles alternated, thus
using a 55ns ram this would give me at least 7 megabytes / sec. this equates to a 140ns write access time to the cpu

the qvga mono needs to read 9600 bytes / frame, so its access to the ram is approx 600kilobytes / sec.
even a color tft qvga with 16 bit color would be only twice this

bob engle
embedded solutions 

>I assume I can get away with a single buffer of display RAM just by
>not clocking the display when I'm writing to the RAM, thereby
>avoiding display glitching and conflicts with the LCD data reads.  I
>assume there's no visible artifact caused by starting and stopping
>>the display clock, does anybody know different?




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