Lpc2000

Hmm, I wrote some interleaving comments of my working out what this does 
(I'm not reflexively familiar with the ARM instruction set yet.  However, I 
get a problem in a different place than you do.  The instruction previous 
to the one you complain about looks wrong to me.  Am I reading this wrong?

At 03:37 PM 1/23/04 -0500, you wrote:

>Why is GNU 3.3.2 generating this code? Am I reading this wrong, or am I 
>using the wrong compiler??
>
>Thanks for any insight!
>
>void Test(unsigned long Base)
>{
>         register volatile U8 * TestP = (volatile U8 *)(Base + 0x5555);
>60000134: E3A01101      MOV      R1,#0x40000000

Why load R1 with anything?

>6000013C: E2802055      ADD      R2,R0,#0x55

R2 = Base +0x55

>6000015C: E2801C55      ADD      R1,R0,#0x5500

R1 = Base + 0x5500.  Just destroyed the first instructions activity.

>60000160: E2810055      ADD      R0,R1,#0x55

Now R0 = Base + 0x5555, the address you are looking for.

>         while (1)
>60000140: E3A01004      MOV      R1,#0x4
>60000164: E3A02004      MOV      R2,#0x4

Both R1 & R2 are 4.  Seems like extra work.

>         {
>                 *TestP = 4;
>60000144: E5C21000      STRB     R1,[R2,#0x0]

This looks wrong.  Store a byte of value 4 at address 4?

>60000168: E5C02000      STRB     R2,[R0,#0x0]   <<-- What is THIS??

*(unsigned char *)(Base+0x5555) = 4     This looks like what you actually want.

This looks like an optimizer gone off the rails.   Have you tried a lower 
optimization level?

Robert

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