Hello Charles,
Thank U!
I found another prob., but now the problem is to change to thumb mode.
How to put the processor from ARM mode to THUMB mode by using ASM
COMMANDS.
LDR R0, =0xE002C000
MOV R1, #10
STR R1, [R0, #0]
LDR R0, =0xE001400C
MOV R1, #0
STR R1, [R0, #0]
Kindly explain me the STATEMENT
STR R1, [R0, #0]
what it does.
upto my knowledge i think it will store the value 0 to R0.
Kindly exaplain me how to pu the processor in thumb mode.
with regds,
Rajendra R
--- In lpc2000@yahoogroups.com, Charles Manning <manningc2@a...>
wrote:
> On Tuesday 29 March 2005 16:53, rockraj_2003 wrote:
> > Hello Friends,
> >
> > I am using IAR EMBEDDED WORKBENCH.
> > The code shown below is produced by the IAR compiler.
> > I want to know what is the offset & how they are using the OFFSET
in
> > PC.
> >
> > Can any one explain me the below program.
> >
> >
> > MEMMAP = 2;
> > LDR R0, [PC,#0x354] [0x68C] =MEMMAP (0xE01FC040)
> > MOV R1, #2
> > STRB R1, [R0, #0]
> >
> > PINSEL0 = 0x0000000A;
> > 0x0000033C 48D4 LDR R0, [PC,#0x350]; [0x690]
=PINSEL0
> > (0xE002C000)
> > 0x0000033E 210A MOV R1, #10
> > 0x00000340 6001 STR R1, [R0, #0]
> >
> >
> > Explain me the LDR & how it points to this address.0xE01FC040
> >
> > LDR R0, [PC,#0x354] [0x68C] =MEMMAP (0xE01FC040)
>
> This is using what is called a literal pool. The actual address is
not part
> of the instruction, but is stored.
>
> When you write code like this you do it as follows:
> ldr r0, =0xE01FC040
>
> The assembler then saves the value futrther on in the .text segment
and sets
> up an instruction to point to that using an offset relative to the
PC.
>
> ie.
>
> ldr r0,[PC,#offset_to_where_value_is_stored]
>
> value_stored_here:
> .word 0xE01FC040
>
>
>
>
>
>
> >
> > kindly help me,
> >
> > with regards,
> > Rajendra R
> >
> >
> >
> >
> >
> >
> >
> > Yahoo! Groups Links
> >
> >
> >Message
Re: REG ARM ASM
2005-03-29 by rockraj_2003
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