Lpc2000

Thank you Ben,
I'm sorry, but it's about the SSP (SPI1) not the UART.
I found no CLR or ENABLE-Bit !
Regard
Gerhard Unrecht

--- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> 
> I noticed the comment on 'proper UART' operation also.
> 
> I have used both the 16c550 and the 16c450 for many years. My 
> recollection is that the FIFO enable bit was supposed to change 
the 
> mode to 16c450 'FIFO-less' operation when disabled; and change the 
> mode to true 16c550 mode when enabled.
> 
> In fact, the National Semiconductor datasheet on the 16c550 says 
the 
> following:
> 
> Bit 0: Writing a 1 to FCR0 enables both the XMIT and RCVR
> FIFOs. Resetting FCR0 will clear all bytes in both FIFOs. When 
> changing from the FIFO Mode to the 16450 Mode and vice versa, data 
is 
> automatically cleared from the FIFOs. This bit must be a 1 when 
other 
> FCR bits are written to or they will not be programmed.
> 
> It was my understanding, according to the LPC2xxx user's manual, 
and 
> datasheet that, (other than not supporting the DMA operation), 
that 
> these UARTS are supposed to be 16c550 clones.
> 
> Ken Wada
> 
> --- In lpc2000@yahoogroups.com, "lp2000c" <lp2000c@e...> wrote:
> > 
> > Beware the fine print that FIFO enable bit must be set for 
proper 
> > operation of the UART!
> > 
> > 
> > --- In lpc2000@yahoogroups.com, "Ken Wada" <kwada@a...> wrote:
> > > 
> > > There are two ways to do this:
> > >   1. Disable the FIFO enable bit on the FIFO control register
> > >   2. Set the Tx FIFO reset bit ont the FIFO control register
> > > 
> > > Ken Wada
> > > 
> > > --- In lpc2000@yahoogroups.com, Gerhard Unrecht <unrecht@p...> 
> > wrote:
> > > > Hey,
> > > > 
> > > > I want to clear the transmit-Fifo, to have a defined state.
> > > > Knows anybody how to do do this?
> > > > 
> > > > Regards
> > > > 
> > > > Gerhard Unrecht
> > > > 
> > > > 
> > > > [Non-text portions of this message have been removed]