Lpc2000

I'm using the SSP port as an SPI and verifing operation by using the
Keil uVision3.  Pclk is set to 15Mhz and with this I'm seeing a clock
of 58,593 out of reset.  After executing SSPCR0 = 0x0E87 (where SCR =
15), the clock rate changes to 3906.  What I'm seeing is 58593/(SCR)

The bit frequency is defined as PCLK / (CPSDVSR * (SCR+1)).
CPSDVSR is set to 0 (default and verified on simulator).

1) What I should see is 58,593 / (0 + 15+1) or 3662
2) And where does 58593 come from?
3) With CPSDVSR and SCR initially set to 0, the clock s/b 15000000
4) It appears that I'm off by 256

Am I looking at something wrong.

   Barry