Lpc2000

--- In lpc2100@yahoogroups.com, capiman@t... wrote:
> So the two operations ( ldr ip, [r0, #0] and strb ip, [r2], #1)
> seems to take in sum 10 cycles.
> Is this correct ?

Purely from a core point of view, on ARM7TDMI a load takes three 
cycles:

1) Sets up the address
2) Reads from memory
3) Writes the data into the specified register

A store takes two cycles

1) Set up the address
2) Write the register value to memory.

Now the second cycle in each case may take a number of processor 
clock ticks depending on the memory system - there may be a delay 
because of a bridge between the AMBA bus and the memory bus, or 
there may be waitstates due to memory setup/access delays.

Something I really need to know is how long the second cycle for I/O 
and RAM accesses takes in processor clock ticks on lpc210x. If 
anyone can help I'd be most grateful.

For a cycle table, I'd suggest downloading the 7TDMI datasheet from 
ARM: http://www.arm.com/pdfs/DDI0029G_7TDMI_R3_trm.pdf - it goes 
into great depth explaining what's going on in each cycle of an 
instruction, allowing you to determine if it will be affected by 
external timing effects.

Peter.