Lpc2000

hi,

Thanks, I know I can set the delays via the BCFG registers, :)
I only wanted to know my idea is possible or not, and max waitstates
will be enough for sed.


Thanks and Regards,
Andrew


--- In lpc2000@yahoogroups.com, "DECwiz \(Fred van Kempen\)"
<decwiz@y...> wrote:
> Of course, the waitstate values have a max of 31, not 15.
>  
> --fred (who'll wake up first..)
> 
> "DECwiz (Fred van Kempen)" <decwiz@y...> wrote:
> That's what the BCFG3 register is for (in your case.)  It sets the
various access
> modes (MW=0, RBLE=0), delays (DLCY=15) and wait states for READ
(WST1=15)
> and WRITE (WST2=15) using:
> 
> #define SET_BCFG(idcy, w1, rble, w2, mw) ( \
>   (((mw) & 0x03) << 28) | (((w2) & 0x1f) << 11) | \
>   (((rble) & 0x01) << 10) | (((w1) & 0x1f) << 5) | \
>   ((idcy) & 0x0f))
> 
> so, BCFG3 = SETBCFG(15, 15, 0, 15, 0);
> 
> in your case.  This gives the slowest-possible 8-bit data/address
bus for
> the chip.  A0 is used as a "command/data" register switch, so,
0x83000000
> is the command register (A0=0) and 0x83000001 is the data register
(A0=1.)
> 
> --fred