Lpc2000

Brian,
 This is how it looks compiled with my tools in the THUMB mode:

//  PLLCFG  = (4 + (2 << 5));

0x0000015E 4812 LDR R0,[PC,#0x048]  ; [0x1A8] =_A_PLLCFG (0xE01FC084)
0x00000160 2144 MOV R1,#68
0x00000162 6001 STR R1,[R0, #0]

My compiler has allocated a constant (address of PLLCFG) at 0x1A8 to 
avoid the limitation of the immediate operand size.  It looks like
your compiler prefers code generation over the data allocation.  Not 
all compilers are made equal ;-)).

Krys

--- In lpc2000@yahoogroups.com, "Brian C. Lane" <brian@s...> wrote:
> y4krys wrote:
> 
> > What is the mode your compiler is set to?  In THUMB mode all data
> > must be 16 bits long.  ARM can add shifts to load some 32-bit
values
> > to registers, but not always.
> > 
> 
> Its in ARM mode right now.
> 
> Brian
> 
> -- 
> -----------------------------------------------------
> Brian C. Lane (W7BCL)                      Programmer
> www.shinemicro.com   RF, DSP & Microcontroller Design