Lpc2000

I get it.
In the register of VPBDIV you can set the XCLKDIV just as VPBDIV.
So XCLK can set as CCLK/1,CCLK/2 or CCLK/4.
Is it right?


--- In lpc2000@yahoogroups.com, Samuel <emddjava@y...> wrote:
> If you place a 10Mhz crystal to the XTAL, the CCLK
> will be 60Mhz, it in the datasheet. then of course you
> have your pheripheral clock...
> 
> 
> --- lpc2100_fan <lpc2100_fan@y...> wrote:
> 
> > Mark,
> > 
> > if I am not mistaken VPBDIV is there to divide CCLK
> > into PCLK
> > (Peripheral Clock).  XCLK is the external clock,
> > which is identical to
> > CCLK if the PLL is not used. Otherwise CCLK = XCLK *
> > PLL factor
> > 
> > Nevertheless I could not find XCLK either in the
> > data sheet or the
> > Users Manual, how did you come up with these terms?
> > 
> > Bob
> > 
> > --- In lpc2000@yahoogroups.com, "Mark Crow"
> > <mcrow@p...> wrote:
> > > Look at the LPC2000 user manual and look up the
> > VPBDIV register.
> > >   -----Original Message-----
> > >   From: lpc2000@yahoogroups.com
> > [mailto:lpc2000@yahoogroups.com]On
> > Behalf Of
> > > fangneu
> > >   Sent: Monday, September 05, 2005 11:50 PM
> > >   To: lpc2000@yahoogroups.com
> > >   Subject: [lpc2000] Who can tell me the
> > relationship between XCLK
> > and CCLK?
> > > 
> > > 
> > >   Thank you very much and I wish that somebody can
> > help me!!
> > > 
> >
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> 
> 
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