Lpc2000

Mark,

missed it, my bad.  Thanks for the clarification!

Bob

--- In lpc2000@yahoogroups.com, "Mark Crow" <mcrow@p...> wrote:
> Only 4 bits of VPBDIV are for controlling PCLK.  The other 4 are for
> selecting the CCLK vs XCLK rate (i.e. XCLK = .25 x CCLK or .5 x CCLK
or 1 x
> CCLK).
>   -----Original Message-----
>   From: lpc2000@yahoogroups.com [mailto:lpc2000@yahoogroups.com]On
Behalf Of
> lpc2100_fan
>   Sent: Tuesday, September 06, 2005 8:05 PM
>   To: lpc2000@yahoogroups.com
>   Subject: [lpc2000] Re: Who can tell me the relationship between
XCLK and
> CCLK?
> 
> 
>   Mark,
> 
>   if I am not mistaken VPBDIV is there to divide CCLK into PCLK
>   (Peripheral Clock).  XCLK is the external clock, which is identical to
>   CCLK if the PLL is not used. Otherwise CCLK = XCLK * PLL factor
> 
>   Nevertheless I could not find XCLK either in the data sheet or the
>   Users Manual, how did you come up with these terms?
> 
>   Bob
> 
>   --- In lpc2000@yahoogroups.com, "Mark Crow" <mcrow@p...> wrote:
>   > Look at the LPC2000 user manual and look up the VPBDIV register.
>   >   -----Original Message-----
>   >   From: lpc2000@yahoogroups.com [mailto:lpc2000@yahoogroups.com]On
>   Behalf Of
>   > fangneu
>   >   Sent: Monday, September 05, 2005 11:50 PM
>   >   To: lpc2000@yahoogroups.com
>   >   Subject: [lpc2000] Who can tell me the relationship between XCLK
>   and CCLK?
>   >
>   >
>   >   Thank you very much and I wish that somebody can help me!!
>   >
>  
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