Lpc2000

OKay, I got it. I was not setting the U1IER. Even though you enable 
uarts to interrupt ( VICIntEnable = ) unless the U0IER and U1IER are 
set, uarts 0 and 1 do not know what to interrupt on. I should read 
more closely.

Thanks,

Mike Haines


--- In lpc2000@yahoogroups.com, "mhaines4102" <mhaines4102@y...> 
wrote:
> I noticed when I posted this that I had 
> VICVectCntl1 = 0x00000027;  // UART1,
> But what is actually in my code is 
> VICVectCntl0 = 0x00000027;  // UART1,
> 
> Which is right. I did get EINT1 working fine, but still noting on 
> the uart.
> 
> Thanks for the help
> 
> Mike Haines
> 
> 
> --- In lpc2000@yahoogroups.com, "mhaines4102" <mhaines4102@y...> 
> wrote:
> > I am having some problems getting the interrupt to fire on the
> > LPC2138 board. I know it is just me missing something, but I 
don't
> > know what I'm missing.
> > 
> > I am using the emulator in the Keil IDE. What I want is when I 
type
> > in the serial area that it fires my interrupt. I don't believe 
it 
> is
> > a limitation of the emulator and I suspect it is my code.
> > 
> > CODE SNIPPETTS
> > *******************************
> > In Startup.s
> > *******************************
> > // Pre-defined interrupt handlers that may be directly
> > // overwritten by C interrupt functions
> > EXTERN CODE32 (Undef_Handler?A)
> > EXTERN CODE32 (SWI_Handler?A)
> > EXTERN CODE32 (PAbt_Handler?A)
> > EXTERN CODE32 (DAbt_Handler?A)
> > EXTERN CODE32 (IRQ_Handler?A)
> > EXTERN CODE32 (FIQ_Handler?A)
> > 
> > // Exception Vectors
> > // Mapped to Address 0.
> > // Absolute addressing mode must be used.
> > 
> > Vectors: LDR PC,Reset_Addr
> > LDR PC,Undef_Addr
> > LDR PC,SWI_Addr
> > LDR PC,PAbt_Addr
> > LDR PC,DAbt_Addr
> > NOP /* Reserved Vector */
> > ; LDR PC,IRQ_Addr
> > LDR PC,[PC, #-0x0FF0] /* Vector from
> > VicVectAddr */
> > ;LDR PC,
> > 
> > Reset_Addr: DD Reset_Handler
> > Undef_Addr: DD Undef_Handler?A
> > SWI_Addr: DD SWI_Handler?A
> > PAbt_Addr: DD PAbt_Handler?A
> > DAbt_Addr: DD DAbt_Handler?A
> > DD 0 /* Reserved Address */
> > IRQ_Addr: DD IRQ_Handler?A
> > FIQ_Addr: DD
> > 
> > ********************************
> > In main.c:
> > ********************************
> > /* initialize the serial interface */
> > PINSEL0 = 0x00050000; /* Enable RxD1 and TxD1 */
> > U1LCR = 0x83; /* 8 bits, no Parity, 1 Stop bit */
> > U1DLL = 97; /* 9600 Baud Rate @ 15MHz VPB Clock */
> > U1LCR = 0x03; /* DLAB = 0 */
> > 
> > VICIntSelect = 0x00000000; // SPI0, I2C UART1, and UART0 are
> >                            // bit 10, 9, 7 and bit 6 = 0
> > VICIntEnable = 0x00000080; // UART1 is enabled
> > 
> > VICDefVectAddr = (unsigned)IRQ_Handler; // Default / Non 
vectored 
> > interrupt handler.
> > VICVectAddr0 = (unsigned)uart1;         // UART1,
> > VICVectCntl1 = 0x00000027;              // UART1,
> > 
> > while(1);
> > }
> > 
> > 
> > void uart1() __irq {
> > switch ( U1IIR ) {
> > case 0x0006:
> >        // case 0110 interrupt - Recieve Line Status interrupt
> >        // check U1LSR for status
> >        // OE if 0x0020 Overrun Error - hold off on writing
> >        // PE if 0x0040 Parity Error
> >        // FE if 0x0080 Framing Error
> >        // BI if 0x0100 Break Interrupt
> > 
> > break;
> > case 0x0004:
> >        // case 0100 interrupt - Receive Data Available interrupt
> >        // Data is available, go read it.
> > case 0x00C0:
> >        // case 1100 interrupt - Character Timeout Indicator 
> interrupt
> >        // This happens when bytes are left in the FIFO but there 
> are
> >        // not enough bytes to trigger an RDA. This means the 
bytes 
> > have
> >        // sat there long enough to time out and tell you to read 
> > them.
> > 
> > case 0x0020:
> >        // case 0010 interrupt - Transmit Hold Register Empty 
> > Interrupt.
> >        // This occurs when the transmit FIFO haddata in it and 
is 
> > now empty.
> > break;
> > case 0x0000:
> >        // case 0000 interrupt - Modem Interrupt
> >        // This occurs when a modem breaks in.
> > break;
> > default:
> > break;
> > }
> > }
> > 
> > Thanks in advance.
> > 
> > Mike H.