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Message

SPI bug : one channel seems to corrupt the other one

2005-10-13 by dukearmlover

Hi all,

I'm using an Olimex LPC2129 board and I'm working on a project that 
uses the two SPI channels.

Did anyone manage to make both SPI channels operate simultaneousy 
(e.g. in master mode), with an interrupt-driven mechanism ?

I tried this, but it seems that the first channel that starts a 
transmission prevents the second one to operate correctly. First 
investigations seem to show that interrupts on the second channel 
never come (the ISR seems never executed, because only the first 
byte 
is sent on the second channel. The interrupt reloads the next bytes 
after the first interrupt has occurred).

I suspect this is linked with the 'known bug' SPI.1. This problem 
causes unintentional clearing of the interrupt flag while writing to 
any SPI register.

But it is not clear what really happens, because there are two 
channels on the LPC. Could it be possible that writing to any 
register 
of SPI 0 or SPI 1 resets both interrupt flags on both channels ? As 
a 
read the errata sheet, it sounds that this was 'channel-wise' true, 
but here ... what happens ?

I changed a little bit one interrupt routine to check the interrupt 
flag of the other channel and to execute the corresponding code if 
set. Things get better, but, depending on how it is done it works or 
not.

Can anyone confirm ?

Any clue ?

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