Lpc2000

lpc2100_fan wrote:

>Tom,
>
>great contribution! It is indeed difficult to count cycles for
>instructions in the ARM. Nevertheless, the LPC2000 family does not use
>a cache. The internal SRAM is something in ARM terms called tightly
>coupled memory (TCM). This offers the same speed as cache but a lot
>less undeterministic behavior. If a real cache gets a cache miss, the
>next instruction could take 20 or more cycles, if there is a branch in
>the SRAM or even hte flash of the LPC2000, it is just the regular 2
>cycles of the branch in SRAM  + 1 cycle for the first instruction from
>Flash.  All subsequent linear instructions either from SRAM or Flash
>will execute the same speed. This is something special in the LPC2000
>series because the bandwidth of the flash based on one fetchcycle
>loads 16 bytes and this can be done every 50 ns. The bandwidth
>therefor is up to 320 MBytes/sec, faster than anything else with flash
>in this market. 
>
>  
>

Cool!   I do see it has some nice performance at 59MHz.  Well beyond the 
14MHz 8051 this board is replacing..  Of course, now that I have more 
Flash, I have put an MMC on it, more serial ports, ...  heh

TomW



-- 
Tom Walsh - WN3L - Embedded Systems Consultant
http://openhardware.net, http://cyberiansoftware.com
"Windows? No thanks, I have work to do..."
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