Lpc2000

--- In lpc2000@yahoogroups.com, Richard Duits <yahoo@r...> wrote:
> Tom Walsh wrote:
> 
>> A lot of Flash does this, while the microcode sequencer inside the 
>> flash memory is busy working with the flash array, it cannot be
>> disturbed by the CPU core reading that same array.  Some flash
>> memories are capable of allowing reading while the sequencer is
>> busy writing / erasing some other part of the Flash array, but
>> these types of Flash are more of an oddity than the normal flash 
>> you find.
>
> I think the LPC2xxx have a flash that can read from the last block 
> while erasing/programming another block, otherwise the IAP routines 
> had be relocated to RAM before using them. It could also be that
> the LPC2xxx has more RAM then specified in the datasheet and that
> the bootcode relocates the IAP routines before jumping to the user 
> program, but this seems more expensive and increases the startup
> time.

Most probably, the whole flash is unreadable during programming, and 
there is no secret RAM.  The User Manual says that the IAP commands 
for write/erase use the top 32 bytes of RAM for execution, and that 
you shouldn't use these bytes if you use write/erase IAP calls in 
your program.  32 bytes should be enough for some Thumb code that 
starts the write/erase, waits for it to finish, and returns to the 
again accessible IAP code in flash.

Some chips, where none of the flash is reserved for the boot block 
(LPC2131, 2132, 2134, 2136, 2141, 2142, 2144, 2146, and probably 
2101, 2102, 2103) do have an extra "secret" flash for the boot loader 
and IAP, see http://groups.yahoo.com/group/lpc2000/message/4636 .

Karl Olsen