Lpc2000

---- Original Message ----
From: "r_bottleneck" <r_bottleneck@...>
To: <lpc2000@yahoogroups.com>
Sent: Saturday, October 29, 2005 1:32 PM
Subject: [lpc2000] Strange LPC2138 EXTINT0 behavior

> I'm rather new with LPC21xx,  therefore I would like to ask the
> experts a question regarding a strange behavior I discovered in my
> application.
>
> I'm using a LCP2138 which gets external interrupts via EXT0 and some
> other internal interrupts. Basically my application works so far.
>
> However, it seems that something strange  happens  if the interrupt
> occurs around the instruction
>   ....
>  VICIntEnClear = INT_EXT0;   // disable EXT0 (INT_EXT0=0x4000)
>     ....
>
> I need to disable the interrupt at the beginning of some certain
> functions and I need to enable the interrupt again at the end of these
> functions.
>
> Thousands of time it works pretty well. The result in this particular
> case however is , the program continues anywhere (I don't know where)
> and after hundreds of microseconds it comes back anywhere in my
> application.

Because of pipelining, the processor probably executes a few instructions
after the VICIntEnClear before it takes effect.  So you can actually get an
EXT0 interrupt some instructions after you have disabled it, and that might
upset your program.

If it is OK to disable all IRQ (or FIQ) interrupts, and not just the EXT0,
it can be done safer (and faster) within the CPU core using MSR:

/* GCC */

/* Set System mode, IRQ and FIQ disabled: */
#define DISABLE_INTERRUPTS asm("msr cpsr_c, #0xDF")

/* Set System mode, IRQ and FIQ enabled */
#define ENABLE_INTERRUPTS asm("msr cpsr_c, #0x1F")

These are guaranteed to take effect immediately, i.e. you won't get an
interrupt between the first and second instruction after the disabling MSR.

If it is not OK to disable all interrupts, then try waiting some clocks
between the VICIntEnClear and your critical section.

Karl Olsen